1. Field of the Invention
The present invention relates to a resistive memory device and a method of writing data in relation to same. More particularly, the invention relates to a resistive memory device in which a single local source line is connected to cell transistors corresponding to the two neighboring rows and a method of writing data in relation to same.
2. Description of the Related Art
Ideal next-generation memory devices would have the high integration density of a Dynamic Random Access Memories (DRAM), the non-volatile storage capabilities of a flash memory, and the high operating speed of a Static Random Access Memory (SRAM). Phase change RAM (PRAM), Nano Floating Gate Memory (NFGM), Polymer RAM (PoRAM), Magnetic RAM (MRAM), Ferroelectric RAM (FERAM) and Resistive RAM (RRAM) have all been discussed as possible alternatives to the implementation of next-generation memory devices.
Amongst these alternatives, the RRAM writes data using a resistance variation associated with a resistance variable element. FIG. (FIG.) 1A illustrates a general cell structure for a RRAM. FIG. 1B shows alternate (<A> and <B>) equivalent circuit diagrams for the general resistive memory cell shown in FIG. 1A.
The resistive memory cell includes a single resistance variable element and a single cell transistor. The resistance variable element includes a first electrode (top electrode) TE, a second electrode (bottom electrode) BE, and a resistance variable material interposed between the first electrode TE and the second electrode BE. The cell transistor includes a first terminal DRAIN, a second terminal SOURCE and a control terminal GATE. The first electrode TE of the resistance variable element is connected to a corresponding bit line (not shown) through a bit line connecting terminal BCT. The second terminal SOURCE of the cell transistor is connected to a common terminal COM.
The resistance of the resistance variable material varies according to a voltage VR or current IR applied thereto. The resistance of a uni-directional resistance variable material varies according to the magnitude of voltage VR or current IR applied thereto while the resistance of a bi-directional resistance variable material varies according to the magnitude and polarity of voltage VR or current IR applied thereto.
FIG. 2 is a graph illustrating model resistance characteristics for a bi-directional resistance variable material. In FIG. 2, the horizontal axis indicates a voltage VR applied to the resistance variable material and the vertical axis indicates the corresponding resistance R of the resistance variable material. α and β are indexes indicating the VR-R characteristics of the resistance variable substance.
When voltage VR greater (more positive) than +βV is applied to the resistance variable material having a first resistance R1, the first resistance R1 of the resistance variable material is changed a second resistance R2. When a voltage VR greater than −αV (more negative) is applied to the resistance variable material having the second resistance R2, the second resistance R2 of the resistance variable material is changed to the first resistance R1. In this manner, logically “high” data or logically “low” data may be written to the resistance variable material by controlling the magnitude and polarity (+ or −) of voltage VR or current IR applied to the resistance variable material. For example, the resistance variable material having the first resistance R1 may correspond to a “high” data state being written to the resistance variable material, and the resistance variable material having the second resistance R2 may correspond to a “low” data state being written to the resistance variable material.
FIG. 3A illustrates a cell array structure of a conventional uni-directional resistive memory device and FIG. 3B illustrates a cell array structure of a conventional bi-directional resistive memory device.
Referring to FIG. 3A, the uni-directional resistive memory device includes first, second, third and fourth bit lines BL1, BL2, BL3 and BL4, first, second, third and fourth word lines WL1, WL2, WL3 and WL4, and resistive memory cells in four rows and four columns. Common terminals (COM41, COM42, . . . ) of the resistive memory cells may be connected if required.
Referring to FIG. 3B, the bi-directional resistive memory device includes first, second, third and fourth bit lines BL1, BL2, BL3 and BL4, first, second, third and fourth word lines WL1, WL2, WL3 and WL4, first, second, third and fourth source lines SL1, SL2, SL3 and SL4, and resistive memory cells in four rows and four columns. In the bi-directional resistive memory device, the word line corresponding to a certain row is activated to turn ON cell transistors corresponding to the word line and voltages are applied to the bit lines and source lines corresponding to the word line such that high-level data or low-level data can be written to the resistive memory cells corresponding to the cell transistors.
In addition to the cell array structures illustrated in FIGS. 3A and 3B, a variety of cell array structures for improving the integration and capacity of resistive memory device are being proposed.